The present invention relates to a multiplexer for multiplexing a plurality of short cells containing low-bit rate information on an ATM connection in communications involving the use of an ATM (Asynchronous Transfer Mode) network.
Generally, communications using an ATM network are carried out by transmitting ATM cells from a transmitting station to a receiving station. The ATM cell consists of a 5-byte header and a payload defined as a 48-byte fixed length data storage area. The payload is stored with user data. The ATM cell is, when transmitted within the ATM network, allocated with one destination (VPI/VCI: Virtual Path Identifier/Virtual Channel Identifier) per connection. Therefore, the header of one ATM cell is stored with information about only one connection.
Incidentally, in the field of mobile communications utilizing a radio system, the information to be transmitted is embedded (cell assembled) in a compression-coded status in the payload of the ATM cell in order to effectively utilize communication bands. The compression-coded information is several bps to several tens of bps, and has an extremely lower bit rate than a transmission speed of the ATM cell. The low-bit rate information takes a relatively long time till it occurs (arrives). Hence, pieces of compression-coded information sequentially occurred are stored directly in the payload of the ATM cell, and, when the payload becomes full of the compression-coded information, the ATM cell is transmitted to the ATM network. If this method is taken, a cellulating process is delayed, i.e., the data transmission is delayed. This delay of data transmission is undesirable because of causing a decline in quality of the communications.
Thus being the case, a transmission method capable of restraining the delay of data transmission due to the delay of the cellulating process and effectively utilizing the transmission bands, is examined in an ATM forum and ITU-T etc. As one of the transmission methods under the examination, there is proposed a method by which the payload of the ATM cell is stored with a plurality of variable-length short cells having a short data length.
FIG. 15 is a conceptual diagram showing a process of multiplexing the short cell in the payload of the ATM cell. Referring to FIG. 15, a short cell 1 consists of a short cell header 2 and a short cell payload 3. The short cell header 2 contains a CID (short cell connection identifier) for identifying a connection of the short cell, and a length indicator (LI) for indicating a payload length of the short cell.
Then, as shown in FIG. 15, the plurality of short cells 1 are multiplexed in the payload 7 of the ATM cell 5 and then transmitted. At this time, one short cell 1 is mapped extending in two ATM cells 5 (which is called an overlap), depending on a position where the short cell 1 is embedded in the payload 7.
Thus, if the plurality of short cells 1 are multiplexed within the ATM cell 5 transmitted on the same connection, a time for which the payload 7 of the ATM cell 5 becomes full of the data can be reduced by the CID attached to each short cell, and hence the delay of the cellulating process, i.e., the delay of data transmission can be restrained.
By the way, there is a CLAD (Cell Assembly and Disassembly) as a technique for storing the payload of the ATM cell 5 with data given from one information source. FIG. 16 is a diagram showing a structure of the CLAD. Referring to FIG. 16, a CLAD 8 is constructed of a data storage buffer 9, a data quantity monitoring unit 10, a reading control unit 11, and an ATM cell header generating unit 12.
The data storage buffer 9 accumulates data inputted from an information source. The data quantity monitoring unit 10 monitors whether or not a quantity of the data stored in the data storage buffer 9 exceeds one cell. When the data exceeding one cell are accumulated, the reading control unit 11 is notified of this fact. The reading control unit 11, upon receiving the notification from the data quantity monitoring unit 10, reads the data for one cell from the data storage buffer 9, and supplies the data to the ATM cell header generating unit 12. The ATM cell header generating unit 12 attaches the ATM cell header 6 to the one-cell data (embedded in the payload 7) read from the data storage buffer 9, thereby generating the ATM cell 5. Then, the thus generated ATM cell 5 is transmitted to the ATM network 13.
The above-described CLAD 8 is, however, structured on the premise that the data stored in the payload 7 of the ATM cell 5 be transmitted on the same connection. Therefore, in the case of the multiplexing the above short cells 1 by use of the CLAD 8, the respective short cells 1 are required to have the same connection information (which are required to be transmitted on the same connection). Accordingly, it was impossible to multiplex the plurality of short cell 1 having different connection data.
Obviation of this problem entails the short cell multiplexer in which the plurality of short cells 1 having the different connection data are multiplexed and stored in the payload 7 of the ATM cell 5, and this ATM cell is transmitted on the same connection.
Herein, for example, the above short cell multiplexer can be actualized by providing buffers corresponding to QOS classes classified according to QOS conditions containing connection statuses (types), designating a reading band for each QOS class, designating a sequence of the buffers-for reading the short cells in accordance with the above designation, reading the short cells 1 one by one from the designated buffer, and multiplexing the short cells.
FIG. 17 is a conceptual diagram illustrating the short cell multiplexer having the construction described above. Referring to FIG. 17, the short cell multiplexer is constructed of an identifying unit 16, a writing unit 17, a storage unit 18, a reading unit 19, and a reading sequence control unit 20. The short cell arriving is inputted to the identifying unit 16.
The identifying unit 16 confirms a process of identifying the connection (such as confirming whether or not the connection is set an, if there is, e.g., “no setting”, disposing of the relevant short cell 1 and so on) on the basis of the CID stored in the short cell header 2 of the short cell 1 inputted to the identifying unit 16 itself. Further, on the basis of the CID of the short cell 1, the identifying unit 16 executes a process of identifying which QOS class the short cell 1 belongs to.
The storage unit 18 is constructed of a plurality of FIFOs (First-In First-Out) 22 (22a-22n). Each of the FIFOs 22a-22n constitutes a storage area of the short cell 1, which correspond to the above-described QOS class. Each of the FIFOs 22a-22n is stored with the short cell 1 having the same CID on the basis of a result of the identification by the identifying unit 16.
The writing unit 17 receives the short cell 1 from the identifying unit 16 via a signal line 16a, and also receives the result of the identification (e.g., a QOS class number of the short cell 1 arriving at the identifying unit 16) by the identifying unit 16 via a signal line 16b. Thereupon, the writing unit 17 switches over its own output in accordance with the QOS class number. The short cell 1 transmitted from the identifying unit 16 is stored in the FIFO 22 of the relevant QOS class by the writing unit 17.
The reading sequence control unit 20 supplies the reading unit 19 with a sequence of reading the short cells 1 stored in the FIFOs 22a-22n in accordance with a predetermined algorithm. for instance, the reading sequence control unit 20 gives to the reading unit 19 an indication of designating the QOS class of the short cells 1 in accordance with the reading sequence corresponding to a sending band preset per QOS class.
The reading unit 19, upon receiving the indication of designating the QOS class from the reading sequence control unit 20, switches over its own output. The short cell 1 is thereby read from any one of the FIFOs 22a-22n, which corresponds to the designating indication. At this time, the reading sequence control unit 20 judges whether or not the payload 7 is full of the short cells read therefrom. If not full of the short cells 1, the reading sequence control unit 20 again gives to the reading unit 19 the QOS class designating indication.
Thus, the reading sequence control unit 20 gives to the reading unit 19 the QOS class designating indication till it is judged that the payload 7 becomes full of the short cells 1. The short cells 1 are thereby sequentially read from the FIFOs 22a-22n and transmitted to the ATM cell header generating unit 12.
The ATM cell header generating unit 12 attaches the ATM cell headers 6 to the plurality of short cells 1 read by the reading unit 19. The ATM cell 5 including the payload 7 in which the multiplexed short cells 1, is thereby structured and transmitted on the same connection.
Herein, there is such a contrivance that a sequence pattern (a QOS class designating sequence pattern) of reading the short cells 1 from the FIFOs 22a-22n, is set as an algorithm for designating the sequence of reading the short cells 1 stored in the FIFOs 22a-22n, and the reading sequence control unit 20 designates the QOS class of the short cell 1 in accordance with this sequence pattern.
FIG. 18 is a conceptual diagram showing the sequence designation control by the reading sequence control unit 20. According to the present method, a storage device (such as, e.g., a memory and a register) 200 possessed by the reading sequence control unit 20 is made to store the reading sequence pattern wherein the QOS class numbers are arranged in a sequence in which to read them. FIG. 18, however, shows an example in which the number of the QOS classes shown in FIG. 17 is given by n=3.
In the example shown in FIG. 18, the storage device 200 is formed with ten setting areas stored with class number each indicating any one of three QOS classes (a class 1, a class 2 and a class 3). Further, a ratio between the QOS classes is set, e.g., such as:Class 1:Class 2:Class 3=5:4:1Then, the class numbers stored in the respective setting areas are arranged from the left side toward the right side on the sheet of FIG. 18 in accordance with the reading sequence. With this arrangement, the reading sequence control unit 20 shown in FIG. 17 repeatedly gives to the short cell reading unit 19 the QOS class designating indication (the indication of reading the short cells 1) in a sequence such as “1→2→1→2→1→2→3→1→2→1” with respect to one cycle. Then, the short cell reading unit 19 reads the short cells 1 from the FIFOs 22a, 22b and 22c (FIFO 22n) in accordance with the above sequence pattern.
There is, however, a problem inherent in the method shown in FIG. 18. Namely,according to the method shown in FIG. 18, it is predetermined how broad the reading band is set per QOS class, and the band is determined depending on how many times the QOS class number is designated in the above-described reading sequence pattern. In the example shown in FIG. 18, if a reading speed is set to 10 Mbps on the whole, the class 1 is designated five times during one cycle of the memory for designating the reading sequence, and hence the reading band of, e.g., the class 1 is given by 10 Mbps×5/10=5 Mbps. Accordingly, for minutely controlling the reading band, it is required that the number of designations in the reading sequence pattern be set as large as possible. This setting involves the use of a memory area of a large capacity, and consequently there arises a problem of causing a rise in the costs for the hardware.
Further, the number of QOS classes designated during one cycle of the reading sequence pattern is conditioned by an accuracy of the reading band. According to the method shown in FIG. 18, the QOS class is designated ten times during one cycle of the reading sequence pattern. Therefore, a reading speed of the short cell 1 (the short cell of the class 3 in the example) read only once during one cycle becomes a minimum bit rate. That is, in the example shown in FIG. 18, the minimum bit rate is 1 Mbps, and a minimum bit rate lower than 1 Mbps can not be set. Moreover, according to the method exemplified in FIG. 18, there is no alternative but to set the bit rate on the unit of only 1 Mbps.
Furthermore, there might be a case of requiring a change in the band for reading the short cell 1 in accordance with an increase or decrease in the number of connections of the short cells 1. According to the method shown in FIG. 18, however, the process of changing the reading band needs resetting the sequence of the QOS class number and the number of QOS class numbers in the reading sequence pattern. It is therefore extremely difficult to execute the process of changing the setting of the reading band.